[Tfug] Ethernet frame "immutables" wrt switch silicon

[Zack Breckenridge]

This is an interesting question... I don't have your answer, but it's
fun to speculate. From Wikipedia:

"A frame starts with a 7-byte preamble and 1-byte start frame
delimiter (SFD)...the corresponding hexadecimal representation is 0x55
0x55 0x55 0x55 0x55 0x55 0x55 0xD5.

PHY transceiver chips used for Fast Ethernet feature a 4-bit (one
nibble) Media Independent Interface. Therefore the preamble will
consist of 14 instances of 0x5, and the start frame delimiter 0x5 0xD.
Gigabit Ethernet transceiver chips use a Gigabit Media Independent
Interface that works 8-bits at a time, and 10 Gbit/s (XGMII) PHY works
with 32-bits at a time."


Then there's the rest of the frame, and an interframe gap. So what
happens when some "non conforming" hardware ignores the interframe
gap, or somehow mangles/overlaps frame start sequences, etc? I'm
willing to bet this "smallest" frame portion is undocumented/assumed
for the obvious reason that manufacturers aren't handling all of the
possibilities.. It might be a fun hardware experiment to see how
different switches react :)


On Sat, May 11, 2013 at 1:50 PM, Bexley Hall <bexley401 at yahoo.com> wrote:
> Hi,
>
> [Probably too technical, here, but worth a shot...]
>
> What's the smallest portion (i.e., individual fields) of the ethernet
> frame that switch silicon must recognize?
>
> Then, the more important question, what is the *most* that it can
> ("safely") recognize/act on?
>
> I've started digging through datasheets but this seems to be one of
> those issues where there is a lot "unsaid"/assumed by manufacturers.
>
> Thx,
> --don
>
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